(1) Field of the Invention
This invention relates to an integrated circuit semiconductor device, and more particularly to a method for fabricating an array of memory cells with minimum cell area that are difficult to achieve in the prior art. The method forms a split bit-line structure using electrically conductive sidewall spacers (as bit lines) which allows for improved self-alignment between bit lines and capacitor node contacts, and thereby reduce the memory cell area.
(2) Description of the Prior Art
In recent years the number and density of memory cells on the DRAM chip have dramatically increased. The DRAM chip areas on the substrate consist of an array of closely spaced memory cells with address and read/write circuits along the periphery of the chip. Currently in production there are 64 million memory cells on a DRAM chip with minimum feature sizes less than a half micrometer. The individual DRAM cells are formed from a single access transistor, typically a field effect transistor (FET), and a storage capacitor with a node contact to one of the two source/drain areas of the FET. The capacitor is used for storing information in binary form (0's and 1's) as electrical charge, and the second source/drain area is connected to a bit line that is used to read and write information via peripheral circuits on the DRAM chip. Word lines that also form the FET gate electrodes over the active device are (cell areas) are used to randomly access the individual memory cells.
By the year 2000 the number of memory cells on a DRAM chip is expected to reach 1 Gigabit. This increase in circuit density has resulted from the downsizing of the individual semiconductor devices (FETs) and the resulting increase in device packing density. The reduction in device minimum feature size F is due in part to advances in high resolution photolithography and directional (anisotropic) plasma etching. For example, the minimum feature size F is expected to be 0.25 to 0.18 micrometer (um) for the next product generation. However, it is becoming increasingly difficult to further reduce the unit memory cell size on DRAMs.
This problem is best understood by considering the design layout of the memory cells as shown in FIGS. 1A and 1B of the prior art for two conventional layouts. Shown in FIG. 1A is a top view depicting the layout for a conventional diagonal bit-line (DBL) memory cell design. The layout consist of an array of word lines 40 extending over the active device regions 42 to form the FETs. The bit lines 44 extend diagonally over the bit line contacts 46 to one of the two source/drain areas of each FET, while the capacitor node contact 48 is formed to the second source/drain area. The dashed line 50 in FIG. 1A shows one of the enclosed unit memory cell area. In terms of minimum feature size F, the unit cell area is 2F.times.3F=6F.sup.2. In FIG. 1B is shown a second layout for a conventional folded bit line cell array. The corresponding elements are similarly labeled as in FIG. 1A. In this layout the unit cell indicated by the dashed line 52 requires a cell area of 2F.times.4F=8F.sup.2, and as is clearly seen, requires a larger cell area. In either case, since the mode contact 48 and the bit line 44 lie in the same plain on the chip, it becomes increasingly difficult to make reliable DRAM devices because of photolithographic alignment tolerances and the reduction in minimum feature size F for future product.
Several methods for making DRAM cells with stacked capacitors have been described in the literature. More specifically, Park et al., in U.S. Pat. No. 5,482,886, describe a method for making DRAM capacitors using sidewall spacers in the node contact opening. Another method is described by Kim, U.S. Pat. No. 5,622,883, for making DRAM cells using landing pads for both the bit line and capacitor node contacts. Also in the prior art of the same reference, a method is described for making capacitor node contacts using sidewall spacers. Still another method is described in U.S. Pat. No. 5,409,855 to Jun for making semiconductor devices having capacitors, in which the capacitance is increased while reducing the height difference between the memory cell area and surrounding area on the chip. However, none of the above addresses the problem in reducing the unit cell area.
Therefore there is still a need in the industry to provide a process that forms improved self-aligned node contacts to bit lines for capacitor-over-bit line (COB) DRAM structures with reduced cell areas.